The present invention relates to a method of and an apparatus for demodulating codes or signals transmitted in terms of amplitude components from a transmitting device in an APSK system for conducting an amplitude modulation by setting signal points as information codes on a complex plane representing a signal space of transmission signals onto two concentric circumference with mutually different radii in the complex plane.
Recently, to improve the transmission rate in digital radio communication systems using mobile facilities and terrestrial communication devices, there has been increasingly discussed an amplitude phase shift keying system in which information codes to be transmitted are modulated also in the amplitude direction.
In the APSK system, various methods of allocating signal points have conventionally been known in consideration of an aspect of the power utilization efficiency and the code error rate. For example, there has been known a 16 quadrature amplitude modulation (QAM) system as described in page 30 of the "Digital Radio Communication" written by Masayoshi Muroya and Heiichi Yamamoto and published from Sangyo Tosho Inc. (1985).
In this case, the transmission signal can be generally expressed by points on the complex plane as the signal space or by complex vectors represented by the points.
Under this condition, `Decision Feedback Differential Detection of Differentially Encoded 16APSK Signals` of "IEEE Transactions on Communications, Voll. 44, No. 4, Apr. 1996" has proposed an example of the method of allocating signal points in which signal points are set onto two different circumferences on the complex plane.
FIG. 1 shows an example of setting signal points in the method. As can be seen from this diagram, eight points are placed on an outer larger circumference with diameter D1 and eight points are set onto an inner smaller circumference with diameter D0. Namely, a total of 16 signal points are allocated. The allocation of signal points is an example of the signal point allocation in the 16APSK system in which a hexadecimal value is represented in association with transmission of one of the signals on the 16 signal points.
In the following description, a period in which a signal of the selected signals point is transmitted is referred to as one symbol.
In relation to a general transmission system of the 16APSK system, FIG. 2 shows an example of a modulating section employed on a transmission side and FIG. 3 shows an example of a demodulating section employed on a reception side.
On the transmission side of FIG. 2, digital information codes to be transmitted are supplied to a dividing circuit 1 to be divided into 4-bit codes.
The 4-bit code includes one bit to be fed to an amplitude delay circuit 2 as a code to be transmitted as an amplitude component, and three remaining bits are fed to a phase delay circuit 3 as a code to be transmitted as a phase component.
First, the received code or signal is processed in the circuit 2 as follows.
Incidentally, one of the binary value is expressed as "L (low level: 0)" and the other as "H (high level: 1)" in the following description.
Assume now that code value A(m) of the m-th symbol transmitted as an amplitude component, e.g., code value A(4) shown in FIG. 4A is "H". There is produced code B(4) of FIG. 4B by inverting the code value of the preceding symbol, the (m-1)-th symbol, that is, code value B(3) of the third symbol.
Subsequently, assuming similarly that code value A(m) transmitted, e.g., code value A(4) shown in FIG. 4A is "L", there is produced code B(6) having a value equal to that of code B(5) transmitted as the (m-1)-th symbol, namely, the fifth symbol.
In this case, the circuit 3 conducts processing which is ordinarily executed by a digital transmitting facility in the differential detection system. However, this is not directly related to the present invention and hence will not be described.
Next, a modulating circuit 4 allocates a 4-bit code including a 1-bit code from the circuit 2 and a 3-bit code from the circuit 3 to one of the signal points shown in FIG. 1 to produce a modulated signal of a carrier corresponding to the allocated point so as to transmit the signal via an up converter 5.
In more detail, the circuit 4 allocates a signal point on the circumference of the large circle with radius D1 when the code from the circuit 2 is "1" and a signal point on the circumference of the small circle with radius D0 when the code from the circuit 2 is "0" to generate modulated signals of carriers respectively corresponding to the allocated signal points.
On the other hand, a signal received on a receiving side of FIG. 3 via a down converter 8 is delivered to an amplitude code or signal demodulating circuit 9 and a phase detecting circuit 10 to separately demodulate the amplitude and phase components.
Thereafter, the demodulated signals are again coupled or mixed with each other into a digital information code to be outputted therefrom.
In the operation, the processing executed by the circuit 10 is the processing ordinarily conducted by the digital transmitting facility in the differential detection system as in the case of the phase delay circuit 3. This is hence not directly related to the present invention and will not be described. The processing of the circuit 9 closely related to the present invention will be described in more detail.
The signal inputted to the circuit 9 can be expressed by a complex vector Z(m) on the complex plane of FIG. 1 in which an absolute value R(m) of the vector Z(m) indicates an amplitude of the received signal.
In this situation, to standardize the terminology with respect to the description of the modulator circuit 4 on the transmission side, the absolute value R(m) is represented as the amplitude value R(m).
FIG. 5 shows an example of a conventional amplitude code demodulating circuit 9. In FIG. 5, an amplitude component separating circuit 12 is a circuit which receives a signal from the down converter 8 via an analog-to-digital (A/D) converter, not shown, and then calculates an amplitude value R(m) of the received signal. The value R(m) from the circuit 12 is directly sent to an amplitude ratio obtaining circuit 14 on one hand. On the other hand, the value R(m) is fed via a delay circuit 13 having a delay of a one-symbol period to the circuit 14. In the circuit 14, a current or present amplitude value R(m) is compared with an amplitude value R(m-1) of the symbol older than the current symbol by one symbol period to thereby obtain an amplitude ratio as H(m)=R(m)/R(m-1).
The ratio H(m) has a waveform shown in FIG. 4C.
The obtained ratio H(m) is then fed to an amplitude ratio determining circuit 17 to be compared with predetermined first and second threshold values Hth1=(1+D0 /D1)/2 and Hth2=(1+D1/D2)/2.
First, when there are obtained conditions Hth1.ltoreq.H(m) and H(m)&lt;Hth2, the amplitude is assumed not to have varied so as to produce a code of "L". On the other hand, when conditions Hth1&gt;H(m) and H(m)&gt;Hth2 result, the amplitude is assumed to have varied so as to produce a code of "H".
The waveform of the code A(m)' of the output signal is then as shown in FIG. 4D. As can be seen from this graph, this waveform is substantially equal to that of the signal of code value A(m) transmitted by the m-th symbol as an amplitude component as shown in FIG. 4A.
Consequently, in accordance with the prior art, of the codes transmitted from the circuit 17, those transmitted as amplitude components are demodulated into output signals. Resultantly, there is obtained a function of a demodulating section of the 16APSK system.
Incidentally, as described above, the amplitude code demodulating circuit 9 of the conventional technology requires the amplitude ratio obtaining circuit 14 to execute a dividing operation of H(m)=R(m)/R(m-1) to attain the amplitude ratio. Therefore, in general, the configuration ordinarily includes a digital circuit including an address circuit 15 and a memory, e.g., a read-only memory (ROM) 16 as shown in FIG. 5.
For the ROM 16, there may be incidentally used an ROM table. The address circuit 15 includes, for example, flip flop circuits 15a and 15b respectively receiving amplitude values R(m) and R(m-1) respectively from the circuits 12 and 13 and a latch circuit 15c to latch data 16c read from the ROM 16. The values R(m) and R(m-1) respectively from the circuits 12 and 13 are used as addresses 16a and 16b to access the ROM 16 to obtain the amplitude ratio R(m)/R(m-1) therefrom. Namely, there are beforehand stored the amplitude ratios corresponding to all combinations of the amplitude values R(m) and R(m-1) in the ROM 16. The ratio 16c (H(m)) thus read from the memory is stored in the latch circuit 15c to be outputted therefrom to the amplitude ratio determining circuit 17.
In this connection, the amplitude of the received signal successively varies in accordance with a level of reception. Moreover, when the codes or signals are transmitted by using also the amplitude component as shown in the signal allocation diagram of FIG. 1, the level comparison is required to be exactly conducted also for the amplitude level.
Therefore, when the number of bits is small in the analog-to-digital signal conversion by the A/D converter in the configuration, the level resolution becomes coarse and there appears a large rounding error, which easily results in a code error in the demodulated code.
In consequence, at least eight bits are required for the digital signal undergone the A/D conversion. If possible, ten or more bits are desirable.
However, for example, even when eight bits are assigned to the digital signal, the dividing operation using the ROM 16 requires that the address is specified by a total of 16 bits including eight bits indicating the amplitude value R(m) and eight bits indicating the amplitude value R(m-1) to read the value of the quotient stored at the specified address. As a result, in the prior art, even when the necessary minimum value of bits, i.e., eight bits are assigned to the signal, there is adopted an ROM having a storage capacity of EQU 256 bytes.times.256 bytes=65,536 bytes.apprxeq.66 kilobytes.